December 02, 2004 -- Reducing on-chip power consumption has become a critical challenge for the nanotechnology era. The traditional trade-offs between performance and area are now being compounded by the addition of power into the equation.
Problems relating to power consumption are not only applicable to the battery powered, handheld and mobile applications, but everything targeting 90nm and beyond, where the power influences designs not only in terms of time to market, but also for cost and reliability.
By Pete Bennett. (Bennett is a Chief Consulting Engineer for Cadence Engineering Services.)
This brief introduction has been excerpted from the original copyrighted article.