Page loading . . .

  
 You are at: The item(s) you requested.Thursday, May 23, 2013
Accurate Power-Analysis Techniques Support Smart SOC-Design Choices  
Publication: EDN Magazine
Contributor: Synopsys, Inc.
 Printer friendly
 E-Mail Item URL

December 7, 2004 -- As power consumption becomes increasingly critical for both portable and nonportable applications, accurate techniques for predicting an SOC's (system on chip's) power have become essential. Designers need to know, for example, whether a mobile-phone SOC requires both voltage and frequency scaling or whether a network-router SOC consumes as much power as a desk lamp. A designer can make these determinations only by estimating a design's power consumption and intelligently applying power-saving methods. Conducting power analysis throughout the flow enables designers to address power issues early on and avoid the lengthy iterations caused by redesigns required to meet power budgets.

By Jim Flynn. (Flynn is a senior IC designer with Synopsys Professional Services.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: EDN Magazine, Synopsys, power analysis, power optimization,
564/10543 12/7/2004 10399 993


Designer's Mall
0.1875



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.5