December 16, 2004 -- The continuing advancements in semiconductor technology have led to production flows for 130nm, 90nm and below, enabling 40 million-plus gate chips to be reliably manufactured. This article explores the methodologies and tools required to predictably design and verify the type of combined hardware/software system that can be implemented today on a single chip within a reasonable timeframe.
Many have recognized the need for electronic system-level (ESL) solutions that address the design and verification complexity on a level of abstraction above RTL. However, exactly which key technologies and methodologies make up these ESL solutions is still under debate.
This article looks at strategies and practices to successfully design the products powered by these large and complex system-on-chip (SoC) designs. The discussion centers around four key aspects: specification, architecture design, software, and re-use and intellectual property (IP). The article also looks at the increasingly central role functional verification plays, identifies critical success factors for electronic system-level tools that can help automate the design/verification flow, and describes how these aspects come together in a coherent solution.
By Markus Wloka and Guy Shaviv. (Wloka is director of R&D for the Synopsys Verification Group in Herzogenrath, Germany and Shaviv is vice president of engineering at Virtio Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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