January 17, 2005 -- One of the biggest challenges of system-on-chip (SOC) designs is that different blocks operate on independent clocks. Integrating these blocks via the processor bus, memory ports, peripheral buses, and other interfaces can be troublesome because unpredictable behavior can result when the asynchronous interfaces are not properly synchronized.

Checking for correct synchronization usually is a time-consuming, manual design process. Often, many possible problems with clock domain crossings (CDCs) are overlooked, resulting in major downstream design problems.

A number of tools have come on the market to identify problems with CDCs. Unfortunately, these tools frequently report hundreds of apparent problems, many of which are often spurious. And this is for structural CDC analysis alone. If you want to check more deeply, assertions must be added to the design. At that point, the number of false errors multiplies, as does the time it takes to go through these and find the real problem spots.

There is a way to make this process less painful. It requires a clear discipline for synchronization and a CDC analysis methodology that works smoothly with inevitable ECOs (engineering change orders) in the design. Also, your CDC tools must support methods to easily reject false negatives and support waiver techniques which do not need to be re-generated on each design ECO.

By Bernard Murphy. (Murphy is chief technology officer at Atrenta, Inc.)