September 1, 2004 -- With the advent of nanometer technologies (130 nanometers and below), significant changes are taking place in the normally staid world of automatic test pattern generation (ATPG).
First, the long-anticipated day when the test vectors for a chip no longer fit on the existing testers is finally at hand-at least for many of the larger 130-nanometer chips, and perhaps for a majority of the larger 90-nanometer chips as well. The response of the ATPG vendors has been to introduce test compression products using many of the basic ideas introduced by IBM at the International Test Conference in 2000. Compression is necessary for many nanometer chips, as we’ll discuss later.
Second, process advances including copper wiring and low-K dielectric have changed the frequency of various defect mechanisms. Today, defects tend to alter the timing of the circuit instead of changing the function, with an increasing majority of defects now located in the interconnection wiring. Resistive opens and resistive shorts alter the time constants inherent in CMOS logic.
By Carl F. Barnhart. (Barnhart is the Core Competency education lead and an architect for the Design for Test Synthesis products at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Chip Design Magazine website.
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