August 1, 2004 -- As ICs marched down the technology path from 1.0 to 0.18 µm, SoC designers and their customers enjoyed faster and more complex IC, without a significant increase in power consumption. But at 130 nm and below, the cost of developing SoCs at 130 nm significantly increased, particularly in masks and NRE costs. In addition, more designs were targeted for mobile applications running off batteries resulting in new design constraints for both dynamic and static power.

Finally, the physics of the silicon (particularly in the power part of the equation) started to work against the engineer. However, the increase in leakage current was most critical.

Thinner gate oxides and lower threshold voltages (0.6 V) result in a significant increase in leakage current and static power consumption. There are, in total, seven additional secondary sources of leakage current, all of which get worse at 130 nm and even more so at 90 nm and 70 nm. Power is now a crisis in nanometer SoC design.

With a challenge as great as this, many companies, in all areas of the design supply chain, are attacking the issue of nanometer power consumption. While individually effective in their own target areas, the current solutions really only provide a partial solution to the problem.

By John A. Ford. (Ford is VP of Marketing at Virtual Silicon Technology, Inc.)