May 2, 2005 -- Algorithmic synthesis helps hardware designers build and verify hardware more efficiently, giving them better control over optimization of their design architecture. The starting point of this flow is a subset of pure C++ that includes a bit-accurate class library. The code is analyzed, architecturally constrained, and scheduled to create synthesizeable HDL. Verification of this RTL is also an important part of the design process.
In a traditional design flow, crafting the hardware architecture and writing VHDL or Verilog for RTL synthesis requires considerable effort. The code must follow a synthesis standard, meet timing, implement the interface specification, and function correctly.
Given enough time, a design team is capable of meeting all these constraints. However, deadlines imposed by time to market pressures often force designers to compromise in area by re-using blocks and IP that are over-designed for their application.
By Bryan Bowyer. (Bowyer is a technical marketing engineer in Mentor Graphics' High-level Synthesis Division.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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