March 4, 2003 -- "As the challenges of network execution time reach new heights, the question of integrating synthesis and design-for-test (DFT) in the fabrication of high density networking devices merits reassessment.
"The challenges that prompt this reassessment come from many directions: product design requirements, semiconductor process technology, and design tools, for instance. The present development wave in networking has a heavy emphasis on features. Voice over Internet Protocol (VoIP) and security are two areas beyond basic quality of service functions that are being heavily invested in at this time. Meanwhile, a new wave of performance-driven products will begin to enter the design stage. So, economics dictate that more transistors must be integrated at lower cost."
By Pradeep Fernandes and Ron Press. (Fernandes is Vice President, Product Engineering, Get2Chip, Inc.; Press is Technical Marketing Manager, Mentor Graphics, Inc.)
This brief introduction has been excerpted from the original copyrighted article.