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Designing ICs with the "X" Architecture  
Publication: eeDesign (EE Times EDA News)
Contributor: Cadence Design Systems, Inc.
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August 29, 2005 -- The X Architecture represents the pervasive use of both Manhattan and diagonal interconnect on a chip. The interleaving of diagonal and Manhattan interconnect offers the ability to significantly reduce the amount of wiring and vias in a design.

This reduction allows designers to target smaller area or higher performance, improved yield and power savings. This is especially applicable in today’s market demands of ever-increasing functionality packaged in smaller, faster and cheaper ICs.

By Kalyan Thumaty and Robert Lipsey. (Thumaty serves as a Cadence Design Systems Vice President and General Manager, responsible for the X Architecture Division; Lipsey serves as the Methodology Architect, X Architecture, at Cadence Design Systems, Inc.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the eeDesign (EE Times EDA News) website.

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Keywords: eeDesign, Cadence Design Systems, X Architecture, place and route, EDA tools,
563/15883 8/29/2005 9292 745


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