October 24, 2005 -- At nanometer technologies, variability is rapidly becoming one of the leading causes for chip failures and delayed schedules. However, there is significant confusion about the term “variability” in the design community today. Variability refers to the unpredictability, inconsistency, unevenness, and changeability associated with a given nuance. For nanometer design implementation flows, variability is associated with design modes, environmental conditions, manufacturing steps, and device and interconnect behavior.

In this article, we explore different forms of variation, review the challenges involved in modeling variability and discuss the requirements of an implementation system that comprehensively analyzes and optimizes variability.

By Shankar Krishnamoorthy. (Krishnamoorthy brings with him over 13 years of experience in the EDA industry leading world-class development teams. Prior to co-founding Sierra, Krishnamoorthy was at the helm of the Physical Synthesis R&D organization at Synopsys, Inc.)