October 27, 2005 -- As Moore's Law has marched through the 1990s into the new millennium, each process node has brought a doubling of density with increased clock and data-transfer speeds and frequencies. Each node, however, also includes the nasty side effects of faster chip, board, and system di/dt transition-voltage noises, as well as signal jitter. To deal with these side effects, engineers need to know how to correctly bypass and decouple high-speed di/dt transitions to reduce noise that the system contains or radiates in some form of EMI.
To achieve this goal, it is important to devise a method of addressing the issues involved in picking and placing bypass and decoupling capacitors for high-speed digital chips, boards, and systems.
By Barry Caldwell. (Caldwell is with Vitesse Semiconductor Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
