May 2, 2003 -- Designing for lower power has become a critical pre-requisite for a chip's technical and commercial success. The challenge of designing chips with optimum energy density and power consumption threatens to increase design time and, therefore, time to market. Moreover, the consequence of failing to meet the power challenge can be a significant increase in the cost of ownership of both chips and systems.
This article discusses a system-level methodology that reduces — or even eliminates — the design delays associated with the traditional approach to designing for lower power. Power estimation and analysis are performed at the algorithmic and architectural level, enabling significant remedial design modification without significant loss of time. Moreover, optimization at algorithmic and architectural levels can deliver greater savings in power consumption than does that at lower levels of abstraction.
By Wolfgang Nebel and Laila Kabous. (Dr. Nebel is Chief Technology Advisor and Co-Founder, ChipVision Design Systems; Dr. Kabous is Technical Marketing Manager, ChipVision Design Systems.)
This brief introduction has been excerpted from the original copyrighted article.