December 15, 2005 -- In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot to lot. In such a paradise, all chips would meet their predicted design parameters. They would all run at the designers' intended speed, no faster and no slower. All would meet their timing specifications. There would be no clock skew, no IR-drop surprises, and happiest of all, no need whatsoever for pessimistic design approaches.

But we don't live in that perfect world. Trains and planes don't run on time. New cars almost never get the mileage claimed by their makers. And silicon fabrication processes vary, sometimes wildly, and in ways that are maddeningly unpredictable. Circuits can vary from predicted physical values in a number of ways, ultimately affecting the transistors themselves, the wires that interconnect them, or both.

Designers have faced the variability of fabrication processes since day one, and by various means, manage to get around it. Primarily, it's through static timing analysis. But a new generation of static timing analysis is upon us, one that uses statistical techniques to overcome the issues inherent in traditional static techniques. In this report, we'll look at where static analysis has been and where it must go to cope with the complexities of nanometer silicon technologies.

By David Maliniak, Senior Editor, Electronic Design Magazine