December 28, 2005 -- Despite the good efforts of the design community to espouse design-for-reuse as the Holy Grail, what many engineers – including thousands of FPGA designers like you worldwide – do in reality is recycle code. This is no disgrace. Actually, it is very smart. Recycling allows you to quickly fill up those monstrously large FPGAs with blocks of code from previous designs, IP, and your own custom code. While recycling has its advantages, it is recommended that you follow a solid recipe for success in order to evaluate recycled code before using it within your new project.
If you do not follow these simple steps, all the time you thought you would save by recycling the code in your new FPGA could easily be lost trying to get it to work correctly.
This is practical reuse – a working recipe for getting your next design quickly completed by reusing code that already exists at your corporation. And, you will likely find that looking at the problem from a completely different angle will actually lead to more and more reuse in your next projects.
By Tom Dewey. (Dewey is a Technical Marketing Engineer for the HDL Designer Series product line at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.