Self-timed packet-switched networks are poised to
take a major role in addressing the complex system design and
timing closure problems of future complex Systems-on-Chip. The
robust, correct-by-construction characteristics of self-timed
communications enables each IP block on the SoC to operate in
its own isolated timing domain, greatly simplifying the problems
of timing verification. Design automation software can remove
the need for expertise in self-timed design, enabling the on-chip
interconnect to be treated as an additional IP block within a
conventional (synchronous) design flow.
The paradigm shift from viewing the SoC design problem as a
matter of organizing complex hierarchies of buses with multiple
coupled timing domains, where every interface between timing
domains must be verified carefully, to viewing the SoC as a
problem in network design where those timing issues are
automatically isolated, promises significant improvements in
designer productivity, component reuse and SoC functionality.
Access the entire document on the Silistix, Ltd. website.
