January 19, 2006 -- More than ever, power integrity is vital in the successful creation of today's system-on-chip (SoC) designs. That's because excessive rail voltage drop (IR drop) and ground bounce can create timing problems. Also, excessive current can cause electromigration and related thermal effects, leading to chip failures.
The first steps designers must take to prevent these problems are solid power-network planning and implementation. The next step is a good rail-signoff analysis flow to ensure that all power-related issues are resolved. To avoid timing problems and device failure, designers need to analyze an SoC's entire power network to ensure that it provides adequate power integrity.
Obtaining accurate rail analysis requires a good methodology and practical guidelines that expedite the flow. These guidelines include practices such as screening library exchange format (LEF) and design exchange format (DEF) files , creating white-box representations to speed analysis, obtaining toggle-rate information for power analysis, and using electromigration plots to identify IR-drop issues.
While dynamic IR-drop effects also should be considered due to the smaller margins of sub-130-nm processes in the overall SoC power closure, this article provides an overview of a suggested rail-signoff analysis flow for static IR-drop analysis.
By David Stringfellow. (Stringfellow is a staff consultant at Synopsys Professional Services.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Design Magazine website.
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