January 30, 2006 -- Just as floorplanning has become vital to the success of system-on-chip (SoC) design, package-aware I/O planning is essential for meeting cost, time-to-market and performance targets. Without such planning, excessive package complexity can significantly increase product cost ó often pushing a chipís package cost higher than the cost of its silicon.
Additionally, I/O problems may limit performance and go undetected until verification, and the numerous design cycles required to correct the problems may delay time to market by weeks. Even without such problems, the traditional I/O design methodology adds weeks to SoC design schedules.
Package-aware I/O planning can prevent these problems, especially for critical flip-chip implementations. The main capabilities needed for package-aware I/O planning are I/O synthesis, placement, and routing. I/O synthesis creates an optimized I/O plan combined with cost-effective packaging options, while satisfying physical and electrical constraints.
The most important I/O planning concept is that I/O planning must be part of the overall system design flow, so silicon design teams must deal with package-related issues. Silicon designers need not become packaging experts; packaging guidance can be built into design tools. However, silicon designers do need to understand some packaging concepts that have long been ignored. This articles explains those concepts and describes package-aware design methodologies that can help meet todayís product goals.
By Egino Sarto. (Sarto is chief technology officer (CTO) at Rio Design Automation.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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