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Preview USB Performance in an SOC Design Using a SystemC Virtual Platform   Featured
Publication: EDN Magazine
Contributor: STMicroelectronics
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February 16, 2006 -- With more software than ever for system-on-chip (SOC) designs, programmers and system architects face a growing and vexing problem: how to evaluate and optimize software performance early in the design phase, well before silicon is in hand. To solve this problem, programmers are turning to virtual platforms, which use software to model the architecture and functions of the target hardware.

When designers carefully perform this task with the help of other software tools, such platforms are proving to be effective ways to make early assessments of important performance measures related to how well embedded software functions and its interaction with yet-to-come hardware. Virtual platforms can predict CPU efficiency, data-transfer and cache-miss rates, interrupt latency, functional hot spots, and other performance measures.

By Kshitiz Jain, Rohit Jindal, Bhuvan Middha, and Rob Smart. (Jain and Jindal are senior engineers, Middha is a design engineer, and Smart is a design manager at STMicroelectronics.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

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Keywords: EDN Magazine, STMicroelectronics, SystemC, virtual prototyping, transaction level modeling, transaction-level modeling, TLM, system-on-chip, SOC, EDA tools,
575/17982 2/16/2006 9298 831


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