For nanometer designs it is no longer sufficient to just achieve timing closure—a design must also reach signal integrity (SI) closure. SI closure implies that the design is free from SI-related functional problems and meets its timing goals while accounting for the impact of SI.
In the pre-nanometer design era, SI effects were either ignored or analyzed and manually repaired after achieving timing closure. This approach no longer works for nanometer designs because the number of potential SI violations exceeds what can be easily managed in a post-route analyze and repair methodology. The increase in SI problems arises from a number of technology advances including reduced feature sizes, decreases in interconnect pitch, and lower power supply voltages. With each new generation of process technology there is a dramatic increase in onchip
crosstalk noise due to both the increase in the number of wires with a large percentage of coupling capacitance, and the accompanying rise in clock frequencies.
For nanometer designs, SI closure must be managed simultaneously with timing closure. To achieve SI closure a design will need to undergo a number of concurrent optimization steps that prevent, analyze, and repair SI-induced problems. Each phase of the design implementation can be subject to these steps including placement, clock tree synthesis, and final detailed routing.
In applying SI optimizations a number of factors must be considered including the precision of the design data available at each stage of the design process. For example, during physical synthesis, SI optimization based on analysis of estimated routes is misleading as there is not enough wire information available to make the correct choices. Without knowing the wire track assignments and layers it is impossible to predict crosstalk effects. What is required is an implementation solution that continuously converges towards SI closure through increasing model
refinement and the appropriate amount of optimization for the given design phase. The solution must be flexible to permit different design trade-offs for different end market needs and it must be efficient without adding significant