For nanometer designs it is no longer sufficient to just achieve timing closure—a design must also reach signal integrity (SI) closure. SI closure implies that the design is free from SI-related functional problems and meets its timing goals while accounting for the impact of SI.

In the pre-nanometer design era, SI effects were either ignored or analyzed and manually repaired after achieving timing closure. This approach no longer works for nanometer designs because the number of potential SI violations exceeds what can be easily managed in a post-route analyze and repair methodology. The increase in SI problems arises from a number of technology advances including reduced feature sizes, decreases in interconnect pitch, and lower power supply voltages. With each new generation of process technology there is a dramatic increase in onchip crosstalk noise due to both the increase in the number of wires with a large percentage of coupling capacitance, and the accompanying rise in clock frequencies.

For nanometer designs, SI closure must be managed simultaneously with timing closure. To achieve SI closure a design will need to undergo a number of concurrent optimization steps that prevent, analyze, and repair SI-induced problems. Each phase of the design implementation can be subject to these steps including placement, clock tree synthesis, and final detailed routing.