April 13, 2006 -- The system-on-a-chip (SoC) era has reached the point where the assembly of such large, complex chips seems almost rote. From a high level, it would appear to be a formula process: choose a processor, choose a bus, bring together your memories and various peripherals, and that's about it. But integrating semiconductor-intellectual property (IP)—the large functional blocks that comprise these various major elements of an SoC—can indeed be a very daunting task.

When contemplating what steps to take to simplify IP integration, three things come immediately to mind. For one, it certainly helps if IP is packaged and described in a standardized fashion. Then the broadest possible range of EDA tools can readily accept it and be able to transfer those descriptions across the design flow. For another, IP blocks must be able to communicate with each other in the system context. Lastly, the quality and pedigree of IP blocks is critical to design engineers.

In this article, we'll take a look at these aspects of IP integration. There's been movement of late in the standards arena, as well as an upsurge in IP quality. We'll look at the activities of the key organizations attempting to bring about industry consensus on IP standards. New choices abound in terms of tools, methodologies, and architectures for the interconnect, which is the lifeblood of an SoC. We'll also look at IP from the perspective of an implementation flow and the special challenges it can pose.

By David Maliniak, Electronic Design Magazine Senior Editor.