In order to meet flexibility, performance and energy efficiency constraints,
future SoC (system-on-chip) designs will contain an increasing
number of heterogeneous processor cores combined with
a complex communication architecture. Optimal platforms are obtained
by customizing both computation and communication modules
to the application’s needs. In our design flow both kinds of
SoC modules are automatically derived from abstract specifications.
This work focuses on generating the communication adaptors,
which are tailored to the processor as well as to the bus side.
For early system simulation, the adaptors are capable of bridging
an abstraction gap by implementing a bus interface state machine.
The generated processor cores, adaptors and bus nodes are applied
in the exemplary design of a JPEG decoding platform.