May 21, 2003 -- SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along with a rich set of new features for verifying model functionality.
The primary objectives of this article are to present an overview of the features in the SystemVerilog 3.1 standard, and address concerns that perhaps SystemVerilog is not ready for use.
By Stuart Sutherland. (Sutherland is an independent Verilog consultant, and specializes in providing comprehensive expert training on Verilog, SystemVerilog and the PLI.)
This brief introduction has been excerpted from the original copyrighted article.