June 5, 2006 -- While area, timing and power have been the main design objectives for several process generations, the design industry is increasingly focusing on a new goal - yield. Attaining high yield for nanometer designs is a growing challenge. Every design decision and manufacturing process has a potential impact on yield. This is particularly true for the 90-nm technology node and subsequent nodes.
Under the guidance of the foundries, designers today apply various yield optimizations, such as via redundancy, metal fill, design and recommended rules. Currently, design implementation tools follow foundries’ recommendations everywhere in the layout and have no capability to make informed trade-offs. The reason is that, in contrast with other design targets, there is no metric today to assess whether or not these optimizations will even improve yield.
To enable trade-offs between yield optimization techniques, a metric for yield is now essential. However, calculating yield without access to the foundry’s process data is almost impossible. But do designers really need the exact yield value to make informed trade-offs? Could they use a first-order metric that corresponds directly to yield, instead?
A first-order metric for yield
Critical area is the key layout attribute used for measuring a design’s sensitivity to yield loss. Used primarily for particle-related yield modeling, critical area also provides an excellent proxy for other yield-loss mechanisms, such as lithography hotspots.
Critical area is the area in the design where circuit failures are most likely to occur. Random particles can cause two types of circuit failures:
- Shorts: a short occurs when a conductive defect creates an electrical connection between two neighboring wires.
- Opens: an open occurs when a non-conductive defect creates an electrical “break” or disconnect in a signal path.
A random particle will only cause a circuit failure if it lands in a location where it can produce an electrical short between two wires or it can break a wire. The sum of all these locations is called the critical area for that specific particle, as shown in Figure 1.
Figure 1. Critical area definition: the region where the center of the particle must fall to create a short or open circuit.
The value of critical area varies for different particle sizes. For a given layout, the bigger the particle size is, the larger the critical area becomes. The average total critical area can be calculated based on the following formula:
Critical area has a direct impact on yield. Yield is improved by reducing the critical area. Instead of assuming that yield loss may occur anywhere in the layout, critical area can be applied as a yield metric to assess whether or not optimizations will improve yield. Applying such a metric during physical design implementation can help designers predict loss characteristics and improve yield. Let’s take a closer look at how this can be implemented practically.
Critical area analysis engine
To optimize a design for critical area, implementation tools must offer an analysis engine that correlates well with sign-off tools used by foundries. The sign-off tools used at foundries have proven critical area analysis engines that help to ensure a golden level of accuracy.
We validated the correlation between the critical area analysis engine in Synopsys’ implementation tools and in Synopsys’s physical verification tool using several designs. Some of the results are illustrated in Figure 2.
Figure 2. Correlation results — Short Critical Area.
Critical area optimizations
Once the critical area of a routing layer is calculated, the router can apply several optimization techniques to reduce critical area and increase yield. After the optimization step, critical area analysis can validate the effectiveness of the optimizations for yield. The complete optimization flow is illustrated in Figure 3.
Figure 3. Yield optimization flow.
Wires with minimum spacing are susceptible to shorts caused by conductive defects or lithography effects. The spreading of wires has been proven effective in reducing critical area and the potential for short circuits. Density-driven wire spreading can be applied during global route and track assignment to achieve more uniform wire distribution and reduce areas with minimum spacing. Wire spreading can also be applied after the design is fully routed to further increase spacing between wires and reduce critical area as shown in Figure 4.
Figure 4. Wire spreading reduces critical area and yield loss from random defects.
Wire spreading - achieved by pushing wires off-track if space is available - creates a jog in the wire layout and increases the wire length. These changes to the wire layout and length can cause potential lithography issues and increase the probability of an open circuit. Therefore, the router should not spread a wire unless the available space is larger than the minimum jog length recommended by the foundry, as shown in Figures 5, and 6. To prevent timing deterioration, post-detail-route wire spreading should not push wires that are part of timing-critical nets.
Figure 5. Pushing wires off-track while meeting recommended minimum jog length.
Figure 6. Example of half-pitch wire-spreading.
Once the router performs yield optimizations, critical area analysis can validate that the total critical area has been improved and thus the yield has increased. The critical area results in Table 1 show how the short critical area is reduced after wire spreading.
Table 1. Short critical area reduction after wire spreading.
With yield challenges on the rise, it has become a reality that designers need to consider yield early in the design process. Once a post-tape-out step, yield optimizations need to be applied during physical implementation so that they do not affect other design objectives such as timing.
Critical area provides an accurate and proven first-order metric for yield. Implementation tools that incorporate critical area analysis are best equipped to determine which routing optimizations can be applied to improve yield. The analysis has to be fast, so that it does not impact runtime, and accurate, so that it provides results correlated to foundry’s sign-off tools. With the goal of reducing Critical Area, physical design tools can make trade-offs to apply timing-driven yield optimizations in best suitable locations.
By Dr. Frank Lee
Frank joined Synopsys in June of 2002. In his current position as Vice President of R&D, he manages the place and route R&D group for Synopsys' physical design flagship products. Dr. Lee holds a Ph.D. in Electrical Engineering from Carnegie Mellon University and a B.S. in Electrical Engineering from National Taiwan University.
Go to the Synopsys, Inc. website to learn more.