June 26, 2006 -- Knowing where and how to apply power rail analysis can save a great deal of time in power planning and verification. Several key concepts can help, beginning with an understanding of appropriate uses for dynamic and static rail analysis. While both types of analysis deal with IR drop, they differ in important ways, and understanding the differences is vital to getting working silicon.
This article provides a quick overview of these dynamic/static differences as well as offering a number of other methodology tips for power verification. The goal is to make sure your power verification methodology really does provide the verification you need, while eliminating unnecessary verification work.
The first rule of thumb is to remember that analysis is not the solution. Fixing the problem is the solution. By focusing on meaningful design fixes — rather than some arbitrary level of "clean" analysis results — you get the solutions you need faster.
Dynamic or static analysis?
Static power rail analysis evaluates the IR drop caused by high average currents flowing through a design’s resistive power rails and generates the familiar plot shown in Figure 1. This type of power rail analysis has traditionally been used as a signoff analysis at technology nodes above 130nm, where sufficient natural decoupling capacitance from the power network and non-switching logic tames most dynamic transients.
Figure 1. An example plot of static IR drop shows large areas where the VDD power rail differs significantly from the nominal voltage. Such differences are truly significant when they prevent the design from meeting timing.
Dynamic analysis evaluates the IR drop caused when large amounts of circuitry switch simultaneously, causing peak current demand on the power rails. This current demand can be highly localized and brief — within a single clock cycle, and can result in an IR drop that causes additional setup- or hold-time violations. Typically, high IR drop on clock networks causes hold-time violations, while IR drop on signal nets causes setup-time violations.
There is no fixed relationship between static and dynamic IR drop in a design. The peak current waveforms used in dynamic analysis are determined by understanding when circuitry switches and the switching circuitry’s electrical characteristics. As a result, these dynamic waveforms are mostly independent of clock frequency.
In contrast, the average currents used in static analysis are calculated over a period of time, typically a clock cycle, and so vary with clock frequency. In the example shown in Figure 2, the same cell operating at different clock frequencies has different values for average current, but the peak current waveform remains constant.
Figure 2. Static power is calculated by averaging current across a time period, which depends on frequency. Dynamic power is associated with clock edges, so the dynamic current waveform does not change with frequency.
Dynamic and static in the flow
Dynamic analysis starts to become important for designs at 130nm and below. This type of analysis is, therefore, relatively new when compared to static analysis, which has been used for signoff for some time. For today’s designs, both static and dynamic analysis should be utilized from initial floorplanning (power planning) through to sign-off, as indicated in the design flow overview in Figure 3.
Figure 3. This simplified low-power flow indicates the main stages of design where static and dynamic rail analyses are valuable.
Important points to consider when determining your methodology for power rail analysis include:
- Use static analysis to generate robust power rails (widths, vias, etc.).
- Use dynamic analysis to optimize the insertion of de-coupling capacitance.
- Use static analysis to optimize power switch sizes to minimize IR drop.
- Use dynamic power-up analysis to optimize power switch sizes to control power-up ramp time.
- Use both static and dynamic analysis early and late in the design flow.
- Establish IR drop limits based on understanding how IR drop can affect timing.
- Try to optimize for decoupling capacitors early in the flow, since late optimization for de-caps can lead to major re-work.
Using only a dynamic approach to understand your design’s IR drop is not a wise design methodology. If you use only dynamic analysis, you could fight a losing battle throwing de-caps at the big red spot on your IR drop display that is actually caused by poor power rail sizing. Static analysis enables you to detect the cause of the IR drop without confusion.
Most advanced standard cell libraries include a number of differently sized filler cells, and associated de-cap cells that have the same footprint. Once dynamic analysis has shown that additional de-caps are required, the first approach for adding the additional capacitance is to swap filler cells for de-cap cells. If cell swapping does not give you enough de-cap cells, you may face major re-work on your implementation to add the required de-caps.
The challenge in trying to correct dynamic IR drop problems late in the design flow is that the de-caps required to correct dynamic IR drop may require increased space on silicon, which may not be available if your routing utilization is high. Under these circumstances, it makes sense to perform dynamic analysis to optimize de-cap size and location as early as possible in your design flow to “reserve” the required area up-front.
On the other hand, if your routing utilization is lower, you may have room to add de-caps later in the flow. In fact, with loose utilization and using mainstream technology nodes, you might be able to get away without initial power planning to reserve the room for additional de-caps, since swapping filler cells for de-cap cells may address all of your needs. As with many design tradeoffs, though, putting off dynamic analysis until signoff increases project risk.
Good static analysis practices
Early in the design, use static analysis to ensure that your rails are wide enough. Static analysis requires less design data to be completed, so you can run this analysis after placement and prior to signal routing.
Every design suffers from IR drop; the question is whether the IR drop causes the design to fail. It is unusual to see IR drop force the operating voltage so low that a block totally fails. It is much more likely that IR drop causes timing or SI noise issues. With these effects in mind, IR drop limits should be determined from a sound engineering approach based on understanding how IR drop can affect timing and SI noise — and not just by simple guesswork. When IR drop causes timing problems, remember that you can either fix the timing or the IR drop.
To make sure that your analysis results are accurate in the first place, remember to account for manufacturing effects. Variations in power rail resistance play a direct role in determining the amount of IR drop along the rail, so bear in mind that the rails you draw get modified to suit the process technology. Specifically, chemical/mechanical polishing (CMP) smoothes the top of the metal and erodes (wears away) copper more than aluminum. Slotting, the methodology of inserting tall columns of dielectric into wide areas of metal, helps prevent this erosion. To help mitigate the impact of erosion, most advanced process technologies have tightened up their requirements for slotting, now requiring slots at smaller widths of metal.
Good dynamic analysis practices
One concern with running any kind of rail analysis in the design-planning stage is that good test vectors are not yet available for the entire design. Vectors are often available at the block level, however, and they provide a good place to start dynamic analysis.
When vectors are available, they usually aim at toggling nodes for functional verification, so use engineering judgment to assess how well these vectors simulate realistic power-consumption behavior. To see values for power consumption that represent the design’s actual working conditions, you need vectors that mirror these working conditions. At the very least, the vectors need to target simultaneous switching of high-power drivers rather than simply toggling all the nodes. Typically, you need detailed knowledge of a design to understand what vectors to run. Memory designs are the exception, where vector patterns used to check access time with read and write cycles work well.
For full-chip analysis or analysis of ASIC-style designs containing random logic, comprehensive suites of vectors are unlikely to be available, so a vectorless dynamic analysis approach should be considered. This type of analysis uses the timing window information from static timing analysis (STA) to determine when gates switch, and complex algorithms predict what gates are likely to switch simultaneously.
If you use vectorless analysis, it is a good idea to correlate these results with vector-based analysis results and with silicon (if available) to better understand if these results trend to optimism or pessimism. For sign-off, analysis needs to be pessimistic, but too much pessimism results in over-design, so a balance is required. Many designers also run up-front experiments to see what power rail configurations work best for their applications and target fabrication technologies.
Another issue that bears more attention is package loading, which can play a significant role in IR drop transients. Packages add resistance, capacitance and inductance to I/Os. Since this additional loading can make IR drop worse, it should be included in dynamic rail analysis. Due to the complexity associated with mapping chip-package pin names and generating pin models, look for analysis tools that provide easy links to get information from package design tools.
As late as 2005, the vast majority of designs starts were at 130nm and above, so most designers had not yet encountered the most severe power-related challenges that begin to rule design flows at 90nm and below. The rail analysis issues and practices described in this article can help ease the transition to 90nm by focusing engineering attention where it is needed. With more advanced technology nodes, the need for both dynamic and static power rail analysis becomes increasingly critical, so it is worthwhile to begin developing sound methodologies using these techniques.
Power comprises three components:
- Dynamic or switching power to charge/discharge the signal load;
- The cells’ internal power;
- Leakage power.
Leakage power increases significantly at the 90-nm technology node and begins to dominate total power between 65 and 45nm. Leakage power is state dependent; the logic condition of a cell plays a role in determining the related leakage.
Power rail analysis deals with dynamic power and the cells’ internal power. The main inputs to power rail analysis are extracted power rail parasitics, power information and voltage sources. The value for power can be calculated in several ways. Static power estimation uses activity information and signal loading. Specifically, static power is calculated as:
P = 0.5·C·V²·F·A where
C = signal net loading;
V = signal’s voltage;
F = frequency of change;
A = activity rate
For example, consider a signal that has a load capacitance of 1.5pF, transitions from 0 to 1.2V at a base frequency of 100MHz, and has an activity factor of 0.4 (only switches four out of 10 cycles). The static power associated with this signal is:
P = 0.5·1.5e-12·1.2·1.2·100e6·0.4 Watts
Dynamic power estimation results in a power waveform per instance. These waveforms are calculated from the static conditions plus a pre-characterized switching waveform for each cell and input slew rates. The calculations for dynamic power can be seeded with information from vectors, which directly determine which cells switch and when they switch. Dynamic power can also be calculated using a vectorless approach, in which complex algorithms determine which cells switch based on timing window, logic and activity information.
By Peter McCrorie.
Peter is the Product Marketing Director for Design for Manufacturing (DFM) at Cadence Design Systems, Inc.
Go to the Cadence Design Systems, Inc. website to learn more.