Certess is a venture-funded EDA company developing technology concentrating on functional verification. Its technology enables engineers to measure and increase the quality of their verification environment for design blocks and IPs. Analysis by Certess' patent pending technology identifies specific areas of the design where the verification environment is weak. It also delivers to engineers and managers an objective measure of the quality of the verification environment. Based on this measurement, the allocation of verification resources can be optimized which results in reduced time to the desired quality level for all blocks and IPs.