August 1, 2005 -- Integrating IP is rapidly becoming the biggest challenge for ASIC designers. There is simply no way to develop fully reusable hard or soft silicon IP of any reasonable complexity so that system-on-a-chip (SoC) developers could reuse unmodified IP in different designs. The wide variety of design environments, tool sets, and chip test requirements make this goal impossible to achieve.
Yet there is a way to minimize the work that IP integrators must do to reuse that IP. To achieve a detailed ranking for the IP while simplifying reuse, it's vital to carefully evaluate and assure the quality of the IP with the design tools and within the design environment that the IP integrator will use. Unfortunately, this technique for maximizing IP reusability is very time consuming and expensive.
By Elias Lozano and Rajesh Shah. (Lozano is the Senior IP and Analog Manager for Open-Silicon and Shah is the Director of Engineering and IP for Open-Silicon.)
This brief introduction has been excerpted from the original copyrighted article.