September 20, 2006 -- This article discusses the differences between
low power CPLDs with a built-in I/O gating feature, and the various "sleep
modes" used by non-volatile FPGAs. Low power CPLDs with I/O gating have many
advantages over sleep modes, including the ability to use selected portions of
the device. These CPLDs are built on an inherently ultra-low-power patented
technology that reduces standby current to as low as 20 microamps.
The technology, known as Fast Zero Power, enables you to build fast, low
power handheld consumer devices using programmable logic. Internal input/output
(I/O) gating is an advanced feature of these devices that enables the design to
gate out unwanted signals during actual operation, thus saving additional power
from unwanted toggling of I/Os and downstream logic. You have to ability to
select the inputs and outputs for gating, and turn them on and off at will.
By Roger Seaman. (Seaman is a Staff Technical Writer in
Outbound Marketing at Xilinx, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
