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A Holistic Approach to System-Level Design andVverification Success  
Publication: EE Times EDA Designline
Contributor: Cadence Design Systems, Inc.
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October 9, 2006 -- Over the last ten years, electronic design complexity has increased exponentially while design techniques and methodologies have expanded only incrementally. From specification to verification and implementation, the current approach is to have varying teams operate independently on an informal specification and channel of communication. This technique worked previously because overall product advancements had been highly associated with hardware innovations. However, as other criteria become vital in the design chain, a major shift in design activity is occurring. We are clearly moving to a "holistic verification approach" that takes into account all aspects of design such as hardware, software, mechanical, and power to form the basis of system-level design and verification.

Compared with a typical ASIC design, full system-level design and verification demands are at a minimum ten times larger. However, similar to isolated design teams performing specific tasks, the system-level design and verification market is highly fragmented with various niche solutions isolated from each other and not well integrated. As a result, the adoption of full system-level solutions has been painfully slow.

By Ran Avinun. (Avinun is a Marketing Group Director within the verification division at Cadence Design Systems, Inc.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

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Cadence Design Systems, Inc.
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Keywords: EE Times EDA Designline, Cadence Design Systems, electronic system level design, ESL, verification, EDA tools,
575/20758 10/9/2006 10213 557


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