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Test Methods Identify Small Delay Defects   Featured
Publication: EE Times EDA Designline
Contributor: Synopsys, Inc.
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October 30 -- Today's systematic and more subtle random defects are not only decreasing yields, but are also increasing the number of test escapes, or defective parts per million (DPPM) shipped out. One of the biggest challenges for design for test (DFT) and test engineers is how to improve test quality without dramatically increasing the cost of test. At 130nm, DFT-based at-speed testing was adopted as a mainstream test technique to meet DPPM goals. Now at 90nm and below, more advanced at-speed tests are needed to maintain and even improve on the quality levels achieved at 130nm. In this article we will present a revolutionary approach in ATPG technology to improve at-speed testing.

By Cy Hay and Rohit Kapur. (Hay is TetraMAX product manager at Synopsys, Inc. and Kapur is an IEEE Fellow and a Synopsys Scientist.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: EE Times EDA Designline, Synopsys, design for test, DFT, automatic test pattern generation, ATPG, EDA tools,
575/20785 10/30/2006 9326 639


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