February 19, 2007 -- Ten years ago, power was a minor concern for many IC designers. Today, four in five chips have a power budget below 2W. The emphasis on low power is due in large part to the explosion of compact mobile systems, but also to the need to reign in the overall power consumption of large-scale systems such as servers and switches. Yet despite these tightening power requirements, few chip designers have the tools and techniques in place to meet their budgets. Until recently, in fact, few EDA tools were available to assist in low power design.

Fortunately, a new generation of EDA tools and techniques is beginning to change that picture, greatly enhancing designers' ability to estimate power dissipation and achieve power goals. This article describes these new tools and techniques, as well as some promising capabilities which could be delivered in future EDA offerings. One common feature of such solutions is that they enable designers to more effectively tune power characteristics early in the design flow, when the cost of such optimizations is lowest and the impact greatest. Designing for power up front not only saves days or weeks of subsequent design iterations, but allows a degree of optimization that is difficult or impossible to achieve through late-stage changes.

By Dave Allen. (Allen is the product director for power at Atrenta, Inc.)