March 29, 2007 -- Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches such as directed and coverage-driven random simulations, assertion-based verification, and formal analysis are needed to most effectively verify a chip. This article focuses specifically on the technique of formal analysis and discusses how to adopt it efficiently on SOC projects.
By Anders Nordstrom. (Nordstrom is an Architect at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.