March 19, 2007 -- At nanometer technologies, variability is rapidly becoming one of the leading causes for chip failures and delayed schedules. However, there is significant confusion about the term "variability" in the design community today. "Variability" refers to the unpredictability, inconsistency, unevenness, and changeability associated with a given nuance. For nanometer design implementation flows, variability is associated with design modes, environmental conditions, manufacturing steps, and device / interconnect behavior. In this article, we explore different forms of variation, review the challenges involved in modeling variability and discuss the requirements of an implementation system that comprehensively analyzes and optimizes variability.

In order to better understand variability, let us consider the example (Figure 1) of the specifications of a mobile phone chip. The design is required to operate in 3 different modes of operation, satisfy 2 PVT corners and 5 interconnect corners. Further, the implementation of this chip in the hyper-competitive mobile phone market has to be completed in 6 months or less. The challenge of implementation lies in the ability to create a single physical layout that satisfies all the constraints imposed by the different modes of operation with process and manufacturing variation (modeled by the corners) accounted for. There are 20 different mode/corner scenarios where the circuit performance requirements need to be validated.

By Sudhakar Jilla. (Jilla is director of technical marketing at Sierra Design Automation, Inc.)