April 24, 2007 -- Our passion to achieve high quality silicon led us down a new road when it came time for functional verification of a project larger than any previous ASIC in our team's history. In this paper we describe why our functional verification methodology yielded functionally robust silicon that has our customers begging for production parts.

Although we could endlessly blather about our design verification methodology, if our ASIC came back from the fab showing no life or demonstrating mediocre quality, well, the blather would be meaningless, right? But that's not what happened. We plugged our ASIC onto a demonstration board and it worked. After rigorous silicon validation we realized that we have hit the goal to produce robust functional silicon with no surprises! We passionately pursued this goal while deploying Cadence's Specman eRM verification methodology on this PCI Express Switch ASIC project. We would love to take you back into the Lab where we have all 4 ports on our PCI Express switch pumping a huge amount of traffic and driving 8 simultaneous videos on the LCD. Seeing it work is worth a million words and achieving robust functional silicon is priceless!

By Henry Angulo, Asad Khan and Scott Morrison. (Morrison is the lead design verification engineer for digital and mixed-signal IP at Texas Instruments, Inc.; Angulo is a senior member of the Technical Staff at Texas Instruments, Inc.; and Khan is a design verification lead engineer for PCI Express, 1394 and Consumer Electronic Digital Interface Business-related projects at Texas Instruments, Inc.)