May 24, 2007 -- Until recently, low-power digital IC design has been an area for specialist or guru IC designers. However, most IC design engineers will have to learn a variety of low-power-design techniques as ASICs and SOCs (systems on chips) increasingly target processes of 130nm and below. At 130-nm processes, foundries started to employ new techniques and materials, such as low-k dielectrics and copper, in silicon processes to increase design performance. However, smaller geometries, scaled thresholds, and unscaled voltages produced smaller, speedier ICs but produced a nasty side effect: leakage, or static power. By the 90-nm node, power management started to become a huge concern, and, at the 65-nm node, low-power-design techniques are a must.
By Michael Santarini, EDN Senior Editor
This brief introduction has been excerpted from the original copyrighted article.