May 21, 2007 -- Scan compression reduces the amount of data needed for digital IC manufacturing tests, thereby lowering the cost of executing patterns on the tester. EDA solutions for implementing scan compression on-chip are readily available, but how do you measure compression performance among alternative vendor solutions to ensure a reliable, "apples-to-apples" comparison? There are a number of factors to consider. In this article, we focus on three fundamental performance metrics: fault coverage loss, pattern inflation, and area overhead. A closer look at each of these metrics is beneficial because each degrades compression performance and directly increases test costs at any level of compression.
By Chris Allsup. (Allsup is marketing manager for test automation products at Synopsys, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: EE Times EDA Designline, Synopsys, scan compression, design for manufacturing, design-for-manufacturing, DFM, design for test, design-for-test, DFT, EDA tools,
