May 17, 2007 -- As design complexity has scaled upward, the need to provide accurate physical constraints like timing, area, power and port locations have become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
A typical design project goes through 10 or more iterations due to timing constraint refinement. Poor constraints impact the chip quality in terms of area, power, and timing. Subsequently, timing closure takes longer. Worst of all, incorrect constraints could result in silicon failing timing and resulting in a re-spin. There is a critical need for an EDA solution to ensure that correct timing constraints are generated and used in the design flow.
Atrenta's SpyGlass-Constraints is an example of a tool that has successfully provided a validation solution to ensure the correctness, completeness and consistency of the timing constraints through a design flow.
By Ramesh Dewangan. (Dewangan is Product Drector-Constraints with Atrenta, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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