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Verifying Configurable Verification Interfaces Using OCP  
Publication: EE Times EDA Designline
Contributor: Jasper Design Automation
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May 10, 2007 -- The Open Core Protocol (OCP) is a synchronous socket interface specification that is widely used in the semiconductor industry today for system-on-chip (SOC) designs. The flexible nature of the implementation makes it widely applicable to many different hardware applications that require a simple, robust data transfer protocol. The OCP International Partnership, a group that is dedicated to proliferating the OCP standard, estimates that OCP has been used in numerous SOC designs which have already shipped in many hundreds of millions of units. The popularity of this protocol is increasing rapidly as more designers become aware of the benefits of a flexible standard.

Naturally, along with the advantages of flexibility come many variants of the implementation that fall under the official protocol specification. While this makes it easy to adapt the protocol to the individual requirements of a specific design implementation, it does present a challenge for the verification team. Verifying protocol interfaces is a challenging exercise for any verification group. Formal verification of protocols has become far more prevalent in recent years because of its ability to exhaustively remove all doubt of incorrect interface behavior prior to tape-out.

This article presents a basic overview of OCP covering both the basic operation and configuration files. It then introduces a configurable OCP formal verification IP generator that automatically creates appropriate OCP properties for a specific to design implementation of the protocol. These concepts are used to demonstrate a silicon-tested method of developing a verification plan for OCP designs.

By Jay Littlefield and Oystein Kolsrud. (Littlefield is Director of Technical Marketing at Jasper Design Automation and Kolsrud is an Application Engineer with Jasper Design Automation.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Jasper Design Automation
on SOCcentral.com

Keywords: EE Times EDA Designline, Open Core Protocol (OCP), Jasper Design Automation, IP, intellectual property, cores, formal verification, EDA tools,
579/22903 5/10/2007 9155 507
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