June 21, 2007 -- Testing and debugging present different problems. In testing, the goal is to determine as quickly as possible whether the chip is working correctly, with high, but not absolute, certainty. Chip-design teams now universally recognize that doing so requires the addition of DFT (design-for-test) circuitry on the chip, and third-party-tool and IP (intellectual-property) companies can aid in this purpose. Debugging is quite another story.
The goal of debugging is not simply to determine that the chip is not working, but to find out why it is not working. This inquiry is not confined to a few seconds on a test floor, but may last weeks. It is not automatic, but requires the participation of the chip-design team. And it occurs at discrete points in the design cycle: during first silicon bring-up, during reliability studies, and during field failure analysis.
Given this profile, you might think that a good DFT strategy would be sufficient to meet the needs of silicon debugging—and, in fact, it often was. But with the growing complexity of SOC (system-on-chip) designs, leading design teams report that they are dedicating more and more planning, implementation, and silicon area to circuitry that supports debugging rather than test.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.