July 30, 2007 -- For so many designs, the engineer and designer go through an interactive placement and routing, consuming both professional's valuable time. Historically, it is a necessary interaction, yet with time consuming inefficiencies. The original plan provided by the engineer may have been a hand sketch without appropriate scales of components, bus widths or pin outs.
As the designer engages with the design, placement of certain components and interconnect are captured by the engineer using topology planning techniques. Yet, the design is not complete with other components to place and probably other IO and bus structures to capture and all interconnects complete. Like the design engineer, the PCB designer employs topology planning while interacting with both placed and unplaced components. Working this scenario produces the optimum placement and interconnect plan " providing density efficiencies.
As critical and dense areas are placed and topology plans captured, placement may be completed prior to the finished topology plan. Therefore, some topology paths may have to work with existing placement " they're a lower priority, yet still need to be connected.
This article is the second part of the two part article covering Topology Planning and Topology Routing.
By Dean Wiltshire. (Wiltshire is a Product Architect, in the System Design Division of Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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