SOCcentral: Chip & Board Testability Assessment Checklist (ASSET InterTech, Inc. 23859)

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Thursday, May 23, 2013

Chip & Board Testability Assessment Checklist

Company: ASSET InterTech, Inc.

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This document summarizes a checklist of questions to assist testability assessment of a board mostly from a boundary-scan perspective but also from other test perspectives (ICT, FPT, AXI, AOI). The checklist is based on a set of Chip and Board Testability Guidelines, available from the author, also available on ASSET InterTech’s website

Access the entire document on the ASSET InterTech, Inc. website.

E-mail ASSET InterTech, Inc. for more information.

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Keywords: ASSET InterTech, JTAG, boundary scan, design for test, design-for-test, DFT, EDA tools, ASIC design, PCB design,

205/23859 10/3/2007 8308 420

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