| The Open Verification Methodology (OVM), Featured | Company: OVM World
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The Open Verification Methodology (OVM), a joint development initiative between Mentor Graphics and Cadence Design Systems, provides the first open, interoperable, SystemVerilog verification methodology in the industry. The OVM provides a library of base classes that allow users to create modular, reusable verification environments in which components talk to each other via standard transaction-level modeling (TLM) interfaces. It also enables intra- and inter-company reuse through a common methodology with classes for developing stimulus sequences and block-to-system reuse.
Supported on multiple verification platforms, the OVM is the de facto standard methodology, ideally suited to speed verification for both novice and expert verification engineers. Built on the success of the Advanced Verification Methodology (AVM) from Mentor Graphics and the Universal Reuse Methodology (URM) from Cadence, the OVM brings the combined power of these two leading companies together to deliver on the promise of SystemVerilog. The OVM offers established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and integration with other languages commonly used in production fl ows.
 | Access the entire document on the OVM World website. |
| Read more about
OVM World
on SOCcentral.com |
| Keywords: OVM World, Open Verification Methodology (OVM), SystemVerilog, transaction level modeling, transaction-level modeling, TLM, IP, intellectual property, cores, ASIC design, EDA tools,
| | 205/24690 1/9/2008 8683 486 | Add a comment or evaluation (anonymous postings will be deleted)
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