January 24, 2008 -- An unwritten assumption of the chip-design profession is that it is always best to use the newest available process: best for your résumé, and best for the design. The most advanced process you can get will make the chip faster, lower power, and less expensive than that old "mature" process you used last year. Flaws in this reasoning have always existed, but the old rule is now breaking down on a grand scale. Far from assuming that they will use the latest and greatest, today’s design teams find that process selection has in itself become an important early step in the design flow.
The causes for this change are easy to find. Diminishing returns have set in, at least for some kinds of structures, on both performance and die area. A given block in a 65-nm process is no longer automatically smaller and faster than it was at 90 nm. Power no longer decreases monotonically with process geometry. Actual energy consumption today is a complex brew of process, library, and design choices. Seasoning this mix are inscrutable end-user behaviors and a growing list of process variations. The result is often not the pudding the designers had in mind.
So, how are design teams choosing their target processes? A number of designer managers and service providers provided some answers. Despite a variety of environments and viewpoints, some patterns have emerged.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.