January 21, 2008 -- In today's SoC development, tremendous mask costs evince the need for first-pass silicon. The steep growth of verification complexity combined with shortened time to market requirements, necessitates the search for more efficient and automated verification practices.
The automation of Formal Verification (FV) is one possible solution to address the above problematic. Complementary to well-established pseudo-random verification techniques, FV enables the verification engineer (or the designer) to exhaustively prove specific parts of a circuit. This article discusses the automation of FV for bus protocols like OCP.
By Jeroen Vliegen. (Vliegen is a Formal Verification Engineer at Texas Instruments WTBU (France))
This brief introduction has been excerpted from the original copyrighted article.
