March 20, 2008 -- If you are a budding timing-analysis engineer or even a veteran, understanding trip points, which all major timing-analysis tools incorporate, is essential. Engineers use trip points in timing-analysis tools to calculate delay and transition values on the various nodes of a design. Timing-analysis engineers must become familiar with the proper use of trip points, as there are many nuances to using them. If engineers overlook them, these nuances can cause problems late in the SOC (system-on-chip)-design cycle, when they need to address timing. A quick tutorial and a bit of timing tool-script work can make their job easier.
By Sunit Bansal, Ateet Mishra, and Naveen Sampath Krishna. (Bansal is a design engineer focusing on static-timing analysis and timing closure of complete SOCs, Mishra is a design engineer focusing on static-timing analysis and timing closure of complete SOCs, and Krishna is a design engineer responsible for static-timing analysis and timing closure of SOCs. All are with Freescale Semiconductor, Inc.)
This brief introduction has been excerpted from the original copyrighted article.