March 24, 2008 -- In the coming decade, SDRs will drive all types of wireless devices, answering the exploding demand for multi-standard, high-throughput wireless communication. Such SDRs will have rigorous constraints for energy consumption, real-time processing, low-cost fabrication, and short time-to-market design. They will be implemented on multi-purpose, multi-processor System-on-Chips (MPSoCs). But the design of SDRs on MPSoCs brings about a dramatic increase in the complexity of hardware and software design.

A team at IMEC recently took the design complexity hurdle. They designed and demonstrated an SDR on MPSoCs, using advanced methods such as electronic system-level (ESL) design and co-emulation. The team first created a high-level virtual model of the SDR MPSoC. Then, each component of the platform was incrementally refined to the RTL level, verifying each step through co-simulation and co-emulation. State-of-the-art processor design tools were used to further model one of the critical low-power processors of the MPSoC. Also with the ESL tools, the data transfers between the processing cores were optimized to meet the tight timing constraints of baseband processing. The ESL tools helped to achieve an efficient design, especially through the architectural exploration and the early performance assessment.

By Bart Van Poucke, Bruno Bougrad, and Jan Provoost. (Van Poucke is a Technical Business Manager within IMEC, Bougard is a researcher at IMEC, and Provoost is a scientific editor at IMEC.)