March 24, 2008 -- Is statistical timing analysis really helping anyone, or is it an EDA-industry marketing ploy? This simmering debate within the leading edge of the chip design community bubbled to the surface in the plenary sessions Wednesday during the International Symposium on Quality Electronic Design (ISQED). The topic was the subject of both a lunch-time panel discussion and a plenary paper by one of the founders of the sport, IBM's Chandu Visweswariah.
There was little argument in the panel discussion as to whether statistical timing actually did anything: No one challenged the underlying theory. There was discussion as to whether, and at what node, statistical techniques were necessary. On one hand, predictably, Visweswariah backed the approach, pointing out that IBM now required full-chip statistical timing analysis on all designs at 65 nm, both for timing closure and for sign-off.
On the other side of the discussion, Sequence Design's Rob Matthews argued that at least at 65nm, extracting what he called "statistically accurate corners" could achieve much the same result as statistical timing analysis. He described the technique only briefly, saying that designers extracted corners in the normal way, then applied statistical tools to relax the margins at these corners from the worst-case levels to something approaching 3-sigma levels of variation. Matthews said that NEC had been applying this technique at 65nm on selected, timing-critical blocks, and had achieved 20 to 30% reductions in excess margins.
Cadence's Vinod Kariat added weight on the skeptical side, pointing out that at 65 nm "there is still a lot of spread in techniques. Many 65-nm designs are done without statistical timing," he maintained.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
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