April 22, 2008 -- Modeling interconnect delay during synthesis has always presented a "chicken-and-egg" problem. Synthesis creates logic structures to meet timing goals, and interconnect is now a significant component of path delay, often exceeding 50%. But you can't get the actual interconnect timing before the chip is placed and routed, meaning you need to have already synthesized and created a logic structure. Creating custom wireloads based on a trial place-and-route is ineffective, because once synthesis begins structuring logic differently the logic structure — and therefore the placement and routing topology — will be different from the first model.
The optimal way to model physical interconnect delay is to do the best job possible at each step of the process, while still allowing the full freedom of optimization associated with that level of abstraction. Early on, before gates are created, physical layout estimation (PLE) models can be used to refine the gate creation process. These models should adapt to the ever-changing logic topology and enable full global synthesis optimization. Once gates are created, a technique like silicon virtual prototyping (SVP) can be used to rapidly create an actual implementation of the placement and routing to accurately identify the nets for which timing is physically dependent and cannot be approximated well enough by the early modeling. In essence, the overall picture becomes one of continuous refinement - i.e., dynamic PLE models enable coarse-grained optimization, which in turn are used to create a better logic structure, followed by SVP to refine the timing model for further optimization.
Because today's chips typically contain hundreds of macros scattered throughout the die, logic is rarely placed in uniformly shaped and sized rectangular regions. Plus, all these macros represent routing blockages that lead to detoured routes, congestion, and so on. Consequently, floorplan information is pertinent to any kind of technique where the goal is to model physical interconnect. The question then becomes, given the differing nature of PLE and SVP described above, what floorplan information is needed for each technique?
By Jack Erickson. (Erickson is a Product Marketing Director for synthesis and logic design at Cadence Design Systems, Inc. )
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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