This paper discusses the effect of sequential changes on functional verification. Sequential transformations are typically done at the system-level and RTL design to improve power, timing and area. Several sequential transformations to datapath and control logic are shown. Sequential changes are avoided late in the design process because of their impact on functional verification. Consequently, designers tend to favor datapath and control logic modifications that least disturbs testbenches. However "verification limited design" ties the hands of engineers and sometimes sequential changes cannot be avoided.
This paper introduces a novel solution, sequential equivalence checking, as well as suggestions to improve testbench robustness to minimize impact of sequential changes on functional verification.
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