With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. Though power should be optimized at all stages of the design flow, optimizations in early design stages have the greatest impact in reducing power.

RTL Clock Gating is the most commonly used optimization technique for reducing dynamic power. The challenge of optimizing power by adding clock gating is knowing where and when to insert clock gating. The traditional method of looking at the percentage of registers that are clock gated is not indicative of the power savings because it does not take into account switching activity. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are gated.