June 9, 2008 -- Over the past several years, low-power design has crept up the list of engineers’ concerns and nestled right alongside timing as a major design objective. Several factors are driving low power’s ascent. The explosion in the popularity of cell phones, MP3 players, PDAs and other handheld systems has made extended battery life a major selling point for portable systems. Increasing awareness of global warming and green technology is also fueling the rise of low power’s importance. Even those who debate the veracity of global warming proponents admit that soaring energy costs and geopolitical forces are causing everyone to reevaluate how they consume power. As a result, semiconductor and EDA vendors alike are looking for ways to squeeze as much as they can from tightening power budgets.

"In everything from server farms to the smallest handheld products, performance per watt is taking center stage," says Ahmed Zaidi, general manager for Intel Corp.’s Silicon Organization, Embedded and Communications Group. "Engineers are turning to multi-core architectures and employing concurrent engineering techniques to find ways to control power at every phase of the design cycle. In our lowest power chips, like the Atom microprocessor, we’ve had joint meetings with chip architects and the RTL, power and layout engineers to study power consumption. They take a datapath through a block and see where power’s being consumed. Then they try and come up with a joint solution."

Additional Reading Industry Leaders Define Next Priorities for Low Power Automating Advanced Low-Power Multi-Voltage Design Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design Power Has Consequences, So Chill Out!

For their part, EDA companies are studying ways to automate low-power design. Traditional design techniques, such as clock gating and clock tree synthesis, are being tweaked to ensure that they identify high-power areas in a design and automate the power-reduction process. EDA vendors must ensure, however, that these design tools and techniques fit into existing flows and not adversely affect timing, performance and area.

"Over the past few years, engineers have tried to manually insert low-power structures into their designs, but they often adversely affected functionality," says Anand Iyer, Product Marketing Director of Low Power Solutions at Cadence Design Systems, Inc. "That’s why EDA vendors with a broad range of solutions, as well as smaller point tool providers, are trying to automate the process while still giving engineers ultimate control. One thing is clear. For every watt you save at the chip level, the overall system savings are at least triple that amount. When Google installs a data center, for instance, the cost of the center pales in comparison to the cost of energy it will consume." (Learn more by reading the Cadence/Power Forward Initiative's Practical Guide to Low-Power Design - User Experience with CPF.)

Figure 1. Significant opportunities exist to improve data center energy consumption. Source: "Energy Logic: Reducing Data Center Energy Consumption by Creating Savings that Cascade Across Systems," Whitepaper, Emerson Network Power.

Traditionally, power-saving duties fell to the RTL engineers who introduced clock gating and clock tree synthesis into their designs. Layout, placement and routing engineers also found ways to make the design more power efficient, but these techniques came at the end of the design cycle when there was no room for timing or functionality errors. The drawback to relying solely on RTL engineers for power savings was the lack of visibility into what was really going on in the design.

"At the RTL, power savings were instantiated on a purely pattern-matching process," says Marc Swinnen, Director of Product Marketing at Azuro, Inc. a provider of EDA tools for low power design and clock tree synthesis. "With traditional RTL techniques, there’s no timing or power analysis. There’s no clue as to whether you saved any power and no idea if the gate enable signal is even achievable. When Azuro users get the netlist they see a placed gate view, which includes the placement of clock tree flip flops. After optimization, we might have one flip flop driving 250. That saves power."

Start at the top

Some engineers are realizing impressive power savings by considering low power at the architectural level. Having embraced electronic system-level (ESL) design for other reasons, these engineers are saving power at a very high level, which trickles down to placed gates. ESL proponents claim that considering power consumption at a high level yields benefits that increase dramatically as the design progresses.

Figure 2. Four key steps in lowering power consumption: move power decisions earlier; leverage reuse; provide meaningful data for power tools; and provide constant validation path.

"By working at the architectural level, our customers have seen power savings of up to 60 percent," says Mitch Dale, Director of Product Marketing at Calypto Design Systems, Inc. "If you look at a design from a high level, you can recognize where computations aren’t being used and propagate that information forward or backward to disable idle clock gate registers. Our tool PowerPro CG, takes a synthesizable design, reads it in, applies sequential analysis and looks for opportunities to insert additional enable logic. It then produces an RTL design with enables that won’t adversely affect the functionality of the design." (Learn more by reading Calypto's whitepaper on The Power of RTL Clock Gating.)

Because widespread adoption of ESL isn’t well established, EDA vendors with solutions at the architectural level sometimes have a tough sell. The drawbacks of performing power optimization at the RTL and below, however, are driving innovative customers into adapting ESL to improve power consumption.

"Our tools take SystemC or C++ as input and then output RTL," says Thomas Blaesi, President and CEO of ChipVision Design Systems AG. "The important thing here is to produce RTL that the engineer can read, because many tools produce RTL that the customer can’t read. Our PowerOpt tool enables chip designers to interactively work with the original input (ANSI-C or System-C) via a user guided inter-process scheduler. It automatically implements various micro-architectures, optimizes them for energy consumption, area, and performance (latency), and compares them against each other, thus creating the optimal implementation."

Some engineers are using ESL tools for power optimization in ways that are sometimes a surprise even for the tool vendors. Designers looking at a system at the architectural level know that if they manipulate system structure at a high level, they can reduce power down the line without affecting timing, performance or functionality. They also rely on IP that’s been generated at the architectural level to save precious time to market.

"In a modern SOC, as much as 80% of the design is existing IP, either re-used from previous projects or provided by a third party," says Bill Neifert, Chief Technical Officer at Carbon Design Systems, Inc. "These blocks typically exist only as RTL with no corresponding model for use in virtual platforms. The development of high-level models of this IP, as well as of a customer’s own newly developed IP, presents a challenge to design teams. Significant resources must be allocated to hand developing and validating models for the virtual platform. With our Carbon Model Studio, there’s no need to spend months hand-coding hardware models because they’re created directly from their VHDL and Verilog descriptions."

RTL optimization still key

Though ESL is steadily gaining a foothold in mainstream low-power design, most engineers still work on incorporating low-power structures at the RTL, an area where they’re most familiar. For their part, EDA companies are providing solutions to help engineers analyze and improve power consumption at the RTL.

"Our customers tell us that 60 to 80% of their power savings can be realized at the RTL," says Vic Kulkarni, president and CEO at Sequence Design, Inc. "They’re finding that clock structures consume about 60 percent of a system’s power, followed by 20 to 30 percent by datapath, with control logic and high-speed I/Os making up the rest."

Figure 3. Sequence’s PowerCanvas quantifies power savings per reduction per module for the designer with other relevant information like area overhead (green box). The RTL designer can then sort and filter the reduction results (upper right). The tool also functions as a worksheet to track and guide RTL changes (middle right) be it automated or manual. Even if the designer chooses to edit RTL manually, PowerArtist provides guidance for the specific RTL changes (lower right). The designer is able to cross-probe reductions to power-annotated schematic logic cones downstream and upstream (upper left) and to the exact line of RTL source code (lower left).

Since power consumption spans almost all structures in a chip, it only stands to reason that broad-based EDA vendors like Cadence, Magma, Mentor Graphics and Synopsys offer solutions that analyze and optimize power in everything from clock trees to I/Os. Recently, Synopsys introduced its Eclypse low-power solution. According to Synopsys, Eclypse simplifies advanced low-power design and verification by combining and automating a wide array of advanced techniques, methodologies, and standards. The Eclypse Low Power Solution supports the industry-standard Unified Power Format (UPF) language, which is used to capture low-power design requirements. With Eclypse, Synopsys aims to automate many of the power-saving techniques that engineers have manually done in the past.

"Through analysis of simulation results plus the information that’s been captured in the UPF file, we can identify areas where performance isn’t a critical factor and start to improve power consumption there," says Larry Zivolo, Director of Marketing for Synopsys, Inc. Low Power Solutions Group. "In the past, there have been many tools that engineers used to manually reduce power, but they had to choose whether to optimize for power or performance, which could be painful. We start in the blocks where performance isn’t paramount and move on to other areas on the chip to optimize power there. We use a number of advanced techniques, which span everything from clock gating to multi-voltage design."

Figure 4. This graph illustrates the variety of power savings techniques spanning mainstream to cutting-edge solutions. Multi-voltage is a technique whereby voltages are varied dynamically. Higher voltages yield lower leakage current, while lower voltages yield higher performance but also higher leakage currents. MTCMOS is also known as power gating. Power shutdown to the entire block yields the ultimate in power reduction, but engineers must consider the tradeoffs. Multi-voltage with power gating represents a compromise, where you turn off gate clocks when blocks go idle for short periods of time, and power off the entire block when blocks are idle for longer periods of time. Dynamic voltage-frequency scaling is common with the most aggressive designs today and will soon be common on many mainstream designs.

The variety of low-power design techniques that engineers use is increasing every year. They all have one thing in common, namely exhaustive analysis of where power is being consumed, so designers can make the trade-offs to save power where they can. After all, if people are talking on a cell phone, it’s unlikely that they’ll need to use the camera function or even a keypad. Selectively shutting power down to an unused block is important, but designers have to be careful when choosing which blocks to shut down and when. Powering up a block and its associated clock tree also consumes power, so needlessly shutting down blocks that are used often can actually consume more power than if they were left on for a period of time.

"It’s important to take a holistic approach when you analyze your design for power savings," says Arvind Narayanman, Product Director for the Design Implementation Business Unit at Magma Design Automation, Inc. "In addition to considerations about power, area, performance and yield, a designer must use an integrated approach from the architectural level all the way down to placed gates. This lets the designer make 'what-if' trade-offs throughout the design cycle, which can save valuable time, especially right before fabrication when changes are time consuming, expensive and inefficient."

Figure 5. MTCMOS switches to selectively power-down portions of the design when not in use.

As power-saving techniques become more widely used and sophisticated, the amount of power saved is also increasing. With today’s techniques, most of which happen at the RTL, engineers are getting power savings in 10% increments, usually topping out at 40 or 50%. At the system level, the power savings can be even larger.

"You can gain orders of magnitude in power reduction if you start at the highest level," says Glenn Perry, General Manager for Design Creation and Synthesis at Mentor Graphics Corp. "This is a relatively new development, because in the past, most relevant power information wasn’t available until later in the design cycle when the target technology was chosen and place and route information was available." (Read Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design to learn more about Mentor Graphics Corp.'s take on low-power design.)

A good example of saving power at the architectural level is a Wi-Fi device. If the engineers decide on the amount of data compaction early in the design cycle, it can have ramifications later, but a trade-off analysis is necessary. More data compaction means that the send and receive blocks consume less power, but that same compaction takes more processing power. Whether greater data compaction is beneficial is dependent on the target application. Trade-off analysis is key.

Figure 6. Accurate information is paramount when making a trade-off analysis. In this shot, the analysis window is generated from Mirabilis Design's VisualSim. The power consumption is shown on the top-half and the performance (timing and waveforms) in the lower-half. The design under test (DUT) is a multi-core platform targeting wireless and multimedia applications. The VisualSim model behind this report is optimizing the battery discharge using dynamic voltage frequency scaling (DVFS) techniques.

To help with the analysis and power-savings decisions in a design, some silicon vendors are building processors with intelligent functions to decide the minimum number of blocks necessary to perform a task. QuickLogic, Inc., for instance, touts its flexible semiconductor platforms’ ability to direct traffic across buses in the system to realize power savings. Based on programmable logic, its Customer Specific Standard Product (CSSP) contains a power-management block to make power-savings decisions on the fly.

"Our power management controller wakes up the USB only when there’s a call from the processor or USB core," says Stanley Hung, Senior Systems Engineer at QuickLogic. "We also maximize throughput from the USB to the IDE, which allows us to turn off the hard drive more often. In that case, the data actually never crosses the CPU bus, which also saves power. Simply put, the processor is handling the control plane and we’re handling the data plane in our device."

The fact that programmable logic vendors are now concerned about power consumption illustrates how widespread low-power design has become. As FPGAs migrated to 65- and 45-nm process nodes, power concerns quickly became evident. This prompted FPGA vendors, who previously weren’t all that concerned with power consumption, to find ways to drastically cut power, especially in devices used in handheld systems.

"The latest process technologies revealed a nasty and challenging side of physics, namely the drastic increase in static power consumption," says Jim Davis, Vice President of Software Engineering at Actel Corp. "This issue is even worse with FPGAs than ASICs, because standard FPGA architectures weren’t designed with power in mind. Recently, however, power-friendly FPGA architectures have been introduced. With our Igloo families, for instance, we feature several power modes: on, static, idle and Flash*Freeze modes. This means they can operate at 1.5 volts or 1.2 volts for both the cores and the I/Os on the device."

All aboard the power bandwagon